PIC16F639-E/SO【PDF 4/74 页】IC MCU FLASH 2KX14 20SOIC

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Sheet目录3878

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Micrel, Inc.

KSZ8841-PMQL

October 2007

M9999-100407-1.5

Pin

Number

Pin

Name

Type

Pin Function

during read/write operation.

STOPN

I/O

PCI Stop

This signal is asserted low by the target device to request the master device to stop the

current transaction.

IDSEL

I/O

PCI Initialization Device Select

This signal is used to select the KSZ8841-PMQL during configuration read and write

transactions. Active high.

DEVSELN

I/O

PCI Device Select

This signal is asserted low when it is selected as a target during a bus transaction. As a

bus master, the KSZ8841-PMQL samples this signal to insure that a PCI target

recognizes the destination address for the data transfer.

REQN

PCI Bus Request

The KSZ8841-PMQL will assert this signal low to request PCI bus master operation.

GNTN

PCI Bus Grant

This signal is asserted low to indicate to the KSZ8841-PMQL that it has been granted

the PCI bus master operation.

PERRN

I/O

PCI Parity Error

The KSZ8841-PMQL as a master or target will assert this signal low to indicate a parity

error on any incoming data. As a bus master, it will monitor this signal on all write

operations.

DGND

Gnd

Digital ground

VDDIO

3.3V digital I/O VDD

SERRN

PCI System Error

This system error signal is asserted low by the KSZ8841-PMQL. This signal is used to

report address parity errors.

—

No connect

—

No connect

—

No connect

—

No connect

CBE3N

I/O

CBE2N

I/O

CBE1N

I/O

CBE0N

I/O

Command and Byte Enable

These signals are multiplexed on the same PCI pins. During the address phase, these

lines define the bus command. During the data phase, these lines are used as Byte

Enables, The Byte enables are valid for the entire data phase and determine which byte

lanes carry meaningful data.

PAD31

I/O

PCI Address / Data 31

Address and data are multiplexed on the all of the PAD pins. The PAD pins carry the

physical address during the first clock cycle of a transaction, and carry data during the

subsequent clock cycles.

DGND

Gnd

Digital core ground

VDDC

1.2V digital core VDD

VDDIO

3.3V digital I/O VDD

PAD30

I/O

PCI Address / Data 30

PAD29

I/O

PCI Address / Data 29

PAD28

I/O

PCI Address / Data 28

PAD27

I/O

PCI Address / Data 27

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